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a) The host shall drive a data word onto D[15:00].
b) The host shall generate an HSTROBE edge to latch the new word no sooner than t DVS after changing
the state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than t CYC for the
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
c)
frequently than 2t cyc for the selected Ultra DMA mode.
The host shall not change the state of D[15:00] until at least t DVH after generating an HSTROBE edge
to latch the data.
d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst
is paused, whichever occurs first.
Figure 9: Sustained Ultra DMA Data-Out Burst Timing
Note: Data (D15:D00) and HSTROBE signals are shown at both the device and the host to emphasize that
cable settling time as well as cable propagation delay shall not allow the data signals to be considered
stable at the device until some time after they are driven by the host.
6.3.2.4.8 Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The
timing diagram is shown in Figure 10: Ultra DMA Data-Out Burst Device Pause Timing. The
timing parameters are specified in Table 22: Ultra DMA Data Burst Timing Requirements and are
described in Table 23: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has
been transferred.
b) The device shall pause an Ultra DMA burst by negating -DDMARDY.
c) The host shall stop generating HSTROBE edges within t RFS of the device negating -DDMARDY.
d) If the device negates -DDMARDY within t SR after the host has generated an HSTROBE edge, then the
device shall be prepared to receive zero or one additional data words. If the device negates -
DDMARDY greater than t SR after the host has generated an HSTROBE edge, then the device shall be
prepared to receive zero, one or two additional data words. The additional data words are a result
of cable round trip delay and t RFS timing for the host.
e) The device shall resume an Ultra DMA burst by asserting -DDMARDY.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 26 of 76
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